This application claims a priority based on Japanese Patent Application Nos. 2000-131523 and 2000-210687 filed on Apr. 26, 2000, and Jul. 6, 2000, respectively, the entire contents of which are incorporated herein by reference for all purposes.
The present invention relates to a digital data recording and reproducing apparatus, in particular, to a signal processing circuit which effectively carries out signal processing such as reading out from a recording medium by controlling a phase-looked loop circuit and a variable-gain-amplifier with a partial response maximum likelihood decoding (hereinafter abbreviated as PRML), and to a digital data regenerating apparatus using the signal processing circuit.
With increasing recording densities in recording units represented by hard disk drives, various technologies have been devised. In particular, about a recording and reproducing method, the PRML has become generally in use to which technologies in communication field are applied.
The partial response (PR) is a system of reproducing data by actively making use of inter-symbol interference (ISI) (interference between regenerated signals corresponding to bits recorded adjacent to each other) with a necessary signal bandwidth compressed. The system may be further classified into a plurality of classes depending on the way of generating this inter-symbol interference. A PR target for magnetic recording is based on the PR in class 4 (PR4).
In addition, among decoding methods, the Viterbi decoding (ML) is a kind of maximum likelihood sequence estimation system which carries out data regeneration on the basis of information of signal gains over a plurality of time units by effectively making use of disciplined ISI (Inter-Symbol-Interference) of regenerated waveforms.
A system of regenerating data by combining the above described PR and ML is named as PRML.
The above-described PRML are provided in a number of variations depending on disciplined ISI of given waveforms, In particular, in the magnetic disk drive, used are such systems as PRML, EPRML (Extended PRML), EEPRML (Extended EPRML), and MEEPRML (Modified EEPRML).
A digital data regenerating apparatus using the PRML like the above is disclosed in, for example, JP-A-8-287607. In general, in a magnetic disc drive, information in magnetized form is read out as electric signals to be outputted as digitized information by a data regenerating circuit.
Processing corresponding to the above-described PRML is carried out in the data regenerating circuit. A read-back signal, being inputted to the data regenerating circuit, is appropriately processed before being converted to a digital signal by an analog to digital converter. A sampling clock for the conversion is generated in a synchronous signal generation circuit.
The synchronous signal generation circuit is constituted to have a phase error detector, a loop filter, and a VCO. The phase error detector obtains phase error between phases of a sampling timing of a sampled signal and an originally expected correct sampling timing. The loop filter carries out appropriate filtering processing of the obtained phase error signal. The VCO generates the sampling clock while controlling its oscillation frequency on the basis of the output signal of the loop filter.
Here, it is necessary for the synchronous signal generation circuit to generate from the generated signal itself a highly accurate sampling clock in synchronism with the regenerated signal. Moreover, by making the phase error detector provided with a high performance, data regenerating performance can be improved and faulty locking of the synchronous signal can be prevented. Such a phase error detector is disclosed in, for example, JP-A-10-125008 or JP-A-7-192406.
However, even with the phase error detector provided with a high performance, there still remains following problem.
Namely, when degradation of the signal recorded on a recording medium, increase in noise in a signal processing circuit, and an error in parameter setting in the signal processing circuit cause considerable degradation in quality of the signal inputted to the phase error detector, temporary quality degradation in a control signal causes further degradation in quality of the input signal to the phase error detector. This will sometimes induce continuous detection error that leads to further degradation in the control signal. Occurrence of such a phenomenon increases a bit error rate of a signal at the output of the signal processing circuit thereby to degrade the performance of the whole system.
The detection made by a detector in related art, for example, a detector included in a phase control circuit disclosed in JP-A-8-287607, is provided without sophisticated decoding such as the maximum likelihood decoding that requires considerable time delay until the signal is outputted. Thus, no consideration is given to the above problem.
As a countermeasure against the above problem, each of JP-A-10-293973 and JP-A-9-17130 discloses that the output of Viterbi detecting circuit for data regeneration is used as a reference signal for phase comparison. This can sufficiently lower a probability of detection error occurrence to allow the phase error to be accurately detected.
However, detection of data with Viterbi algorithm requires so long a delay time for data detection that no sufficient band can be secured for phase control. Therefore, there arises a problem in that simply adopted Viterbi algorithm will make the control unstable.
Accordingly, it is an object of the present invention to provide a signal processing circuit which can reduce the data error rate therein by using the Viterbi algorithm being adopted.
In order to achieve the above object, the information recording and reproducing apparatus has a data regenerating circuit which regenerates recorded data on the basis of a read out signal read out from a recording medium, a decoding circuit which decodes the recorded data regenerated by the data regenerating circuit, and an interface for outputting externally the recorded data decoded by the decoding circuit.
The data regenerating circuit comprises an analog to digital converting circuit which converts the read out signal from an analog signal to a digital signal, an equalizer which carries out waveform equalization of the read out signal converted to the digital signal, a detector circuit which outputs binary data by carrying out signal detection on the basis of the output signal of the equalizer, and a synchronous signal generating circuit which generates a synchronous signal for determining a sampling timing in the analog to digital converting circuit.
In the preferred embodiment according to the present invention, the synchronous signal generating circuit has a phase error detecting circuit which carries out signal detection of the output signal from the equalizer on the basis of a detection algorithm that provides a shorter response time than that in the Viterbi detector and a higher accuracy than that in signal detection based on a threshold value and detects a phase error on the basis of a result of the signal detection, a loop filter which is connected to the output side of the phase error detecting circuit, and a variable frequency oscillation circuit which generates on the basis of the output of the loop filter a synchronous signal given to the analog to digital converting circuit.
As a different embodiment of the present invention, a signal processing circuit according to the present invention is characterized by comprising a variable-gain-amplifier which adjusts a gain of a regenerated signal regenerated from a recording medium, an analog to digital converter which carries out sampling of the regenerated signal outputted from the variable-gain-amplifier to output a digital data signal, an oscillator which generates a clock signal supplied to the analog to digital converter, a maximum likelihood detector which carries out maximum likelihood detecting about the digital data signal, a decoder which carries out decoding of data recorded on the recording medium from an output value of the maximum likelihood detector, a detector which detects the digital data signal, a first error signal generator which generates a first error signal from the result of the detection of the detector, a second error signal generator which generates a second error signal with a higher accuracy than that of the first error signal, and a control signal generator which generates a phase control signal that controls, on the basis of the first and second error signals and the digital data signal, a gain control signal that controls a gain of the variable-gain-amplifier and at least one of a phase and frequency of the clock signal generated by the oscillator.
In the different embodiment according to the present invention, the second error signal is obtained as a result of detection employing the maximum likelihood detection. More specifically, the second error signal generator carries out maximum likelihood detection about a value obtained from an intermediate stage of a memory path constituting the maximum likelihood detector, with the result thereof used as the second error signal.